The present invention relates generally to decoder circuits, and more particularly to a decoder circuit which is suitable for use in memory cell selection in a memory device.
Generally, a memory device comprises a plurality of word lines and bit lines arranged in matrix form, a plurality of memory cells provided at respective intersection points between the word lines and bit lines, a decoder circuit for performing word line selection, and a decoder circuit for performing bit line selection. Conventionally, in a memory system of the above type, a constant current source circuit which provides a bit current to the bit line group and a switching circuit which provides the bit current to only the bit line which is to be selected, are respectively, separately and independently connected in series in a bit line selection decoder circuit. Accordingly, at least two stages of voltage boosting are required for the transistors which constitute the constant current source circuit and switching circuit, resulting in the inability to obtain low-level biasing. Hence, the margin of allowable variation in the power source output level becomes small, and results in a disadvantage in that stable operation of the memory system can not be guaranteed.